[PPL-devel] IEEE inexact-flag not working on the Alpha (despite -mieee-with-inexact)?

[Roberto Bagnara]

While testing the portability of the Parma Polyhedra Library, Abramo Bagnara
and myself identified the following apparent problem on the Alpha, whereby
the division 2/3 made on floats is flagged as exact.  Here are the details:

$ cat sf.cc
#include <fenv.h>
#include <cstdio>

int main() {
   float x = 2;
   float y = 3;
   feclearexcept(FE_INEXACT);
   x = x / y;
   printf("%d %.1000g\n", fetestexcept(FE_INEXACT) != 0, x);
}
$ g++ -v
Using built-in specs.
Target: alpha-linux-gnu
Configured with: ../src/configure -v --enable-languages=c,c++,fortran,objc,obj-c++ --prefix=/usr --enable-shared --with-system-zlib --libexecdir=/usr/lib --without-included-gettext --enable-threads=posix --enable-nls --with-gxx-include-dir=/usr/include/c++/4.2 --program-suffix=-4.2 --enable-clocale=gnu --enable-libstdcxx-debug --enable-objc-gc --enable-mpfr --disable-libssp --with-long-double-128 --enable-checking=release --build=alpha-linux-gnu --host=alpha-linux-gnu --target=alpha-linux-gnu
Thread model: posix
gcc version 4.2.4 (Debian 4.2.4-3)
$ g++ -mieee-with-inexact sf.cc
$ ./a.out
0 0.666666686534881591796875
$ cat /proc/cpuinfo
cpu                     : Alpha
cpu model               : EV56
cpu variation           : 7
cpu revision            : 0
cpu serial number       :
system type             : Rawhide
system variation        : Tincup
system revision         : 0
system serial number    : AY74642662
cycle frequency [Hz]    : 399642346 est.
timer frequency [Hz]    : 1200.00
page size [bytes]       : 8192
phys. address bits      : 40
max. addr. space #      : 127
BogoMIPS                : 705.16
kernel unaligned acc    : 0 (pc=0,va=0)
user unaligned acc      : 31 (pc=20000074c18,va=87)
platform string         : AlphaServer 1200 5/400 4MB
cpus detected           : 1
cpus active             : 1
cpu active mask         : 0000000000000001
L1 Icache               : 8K, 1-way, 32b line
L1 Dcache               : 8K, 1-way, 32b line
L2 cache                : 96K, 3-way, 64b line
L3 cache                : 4096K, 1-way, 64b line
$

We are not sure if this is a bug in GCC (we did search bugzilla though),
so we decided to post here before filing a bug report.
All the best,

     Roberto

-- 
Prof. Roberto Bagnara
Computer Science Group
Department of Mathematics, University of Parma, Italy
http://www.cs.unipr.it/~bagnara/
mailto:bagnara at cs.unipr.it